62258BR

Title:

Senior PD engineer

Job Description:

Quest Global is an organization at the forefront of innovation and one of the world’s fastest growing engineering services firms with deep domain knowledge and recognized expertise in the top OEMs across seven industries. We are a twenty-five-year-old company on a journey to becoming a centenary one, driven by aspiration, hunger and humility.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible, possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.

As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

Roles & Responsibilities:

• Must have hands-on experience on PNR Suite from Cadence & Synopsys (Innovus & ICC2)

• Strong experience in Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).

Required Skills (Technical Competency):

• The responsibilities will include several of the following, but not be limited to:

• Performing floor-planning and routing studies and implementation at block and full-chip level

• Push down the top-level floorplan and clock to Partition.

• IO Planning and bump planning

• Closely working with Package team and reaching Die file milestones

• Full chip and partition level timing analysis.

• Evaluate low power techniques and power reduction opportunities

• Perform clock distribution design and analysis

• Perform Physical verification activities at full-chip level.

• Drive technical activities of physical design during technology readiness, design & execution

• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience in Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes

• Should have experience in handling >1M instance count, 1 GHz frequency designs

• Should have experience in programming in Tcl/Tk/Perl to automate the design process and improve efficiency

Desired Skills:

• VLSI training certification and working experience with global customers

Auto req ID:

62258BR

Job Type:

Full Time-Regular

Assignment Country:

India

Total Years of Exp:

6 - 9

Education Type:

M.E/M.Tech/MS-VLSI Design & Embedded System

Assignment State:

Karnataka

Assignment Location:

Bangalore (Bengaluru)

Experience Level:

Senior Level